1. Field of the Invention
The embodiments described below generally relate to non-volatile memory devices, and more particularly to reducing the disturbance of threshold voltages when programming such non-volatile memory devices.
2. Background of the Invention
Non-volatile memory devices, such as EPROMs, EEPROMs, and flash memory devices use a threshold Vt of a memory cell to indicate a data value stored in the memory cell. When writing, or programming, a target memory cell, programming voltages are applied to the cell via a word line connected to a control gate of the selected cell, a bit line connected to a drain of the selected cell, and a source line coupled with the source of the selected cell. The combination of programming voltages changes the threshold voltage of the target cell, e.g., by causing Fowler-Nordheim (FN) tunneling or by Channel Hot Electron (CHE) injection of charge into, or out of a floating gate in the selected memory cell.
For example, for CHE injection in a target memory cell, e.g., containing a typical N-channel floating gate transistor, a high voltage is applied to the control gate, a high voltage is applied to the drain, and a low voltage is applied to the source. This combination of voltages creates a large lateral electric field between the source and drain, which generates hot electrons that are injected into the floating gate thereby increasing the threshold voltage level of the floating gate with respect to the control gate. By adjusting the magnitude and/or duration of the programming voltage applied to the control gate, this target cell can be programmed to a desired threshold Vt.
Conventionally, hot electron programming is performed by first ramping up the drain voltage, or the gate voltage. In other words, a low voltage is first applied to the source, and then the drain voltage is increased. Once the drain voltage has reached its target level, the gate voltage can be applied. In other embodiments, the gate voltage can be ramped and then the drain voltage can be applied. Accordingly, there is typically a drain voltage set up time involved with programming a non-volatile memory device.
During programming of a target memory cell, the voltages applied to the drain and a high voltage applied to the control gate for the target memory cell can cause two types of disturbances: (1) create a large voltage difference between the floating gate and drain of unselected memory cells that are connected with different word line but the same drain bit line. This unintended voltage difference between the floating gate and drain of unselected memory cells can induce FN tunneling of electrons into or out of the floating gate, which can disturb the threshold voltages of these unselected memory cells. And (2) create a large CHE current to pre-charge the parasitic array loading through the unselected memory cells connected with the same word line. These two kinds of disturbances of the threshold voltage are often referred to as a program disturb effect.
The FN tunneling current (number (1) above) is exponentially dependent on the electric field in the gate oxide between the bit line coupled with the drain and the floating gate, program disturb will worsen significantly even for small increases in the electric field. If the FN tunneling current is high enough for a long enough period, the threshold voltages of the unselected cells can be lowered significantly, thereby adversely affecting the accuracy of the storage array. If the CHE current created in the unselected cells (number (2) above) is high for a long enough period, the threshold voltage of the unselected cells can be raised significantly, thereby adversely affecting the accuracy of the storage array, especially for multi-level cell (MLC) memory.
Further, the disturbance of threshold voltages can accumulate through repeated programming of memory cells in the same column or row and change the data value stored in unselected cells. Depending on the memory a data value stored in a memory cell can be binary, e.g., a “1” or a “0,” multilevel, e.g., the cell can be programmed to a value from a set of discreet values, or analog, e.g., the cell can be programmed to a value within a continuous range of possible values. For binary memories, the accumulated disturbance of threshold voltages must be relatively large, on the order of a volt or more, in order to change the threshold voltage from a state indicating a first binary value to a state indicating the second binary value; however, for multilevel or analog memories, distinguishable threshold voltage differences for data values can be a few millivolts. Accordingly, even small differences in threshold voltages can result in program disturb.
For multilevel and analog memories, the problem is only getting worse as the channel lengths for conventional devices get shorter and shorter. Accordingly, program disturb is becoming a larger issue as non-volatile memory devices evolve.
The total accumulative disturb due to number (1) above is dependent on the number of cells on a bit line, the right time of a cell, the area in gate oxide thicknesses between the drain and the floating gate, and the drain voltage applied for programming. Thus, program disturb can limit, among other things, the number of cells that are allowed on a single bit line, as well as the thickness of the gate dielectric of the memory cells.
Accordingly, one approach to limiting, or preventing program disturb is to divide larger arrays into several smaller arrays so that fewer memory cells are on the same row or column. In such devices, programming a selected memory cell disturbs fewer unselected memory cells, and the accumulated programming disturb time for each memory cell is reduced; however, including more small arrays has the unwanted effect of increasing the overhead in decoding circuitry required to access the memory cells. This increased overhead results in increased cost and size of the memories.
The total accumulative disturb due to number (2) above is dependent on the number of program shots of the selected cells on the same word lines. Conventional approaches for limiting the pre-charge parasitic loading current involve pre-charging all the parasitic array loading. Other conventional solutions include pre-charging the drain, and in some instances the source nodes of unselected memory cells in order to prevent the program disturb effect. Such solutions, however, increase the pre-charge and set up times and therefore increase the overall programming time. Such solutions also tend to increase power consumption during programming, which can reduce battery lifetimes in portable devices.
Other solutions to the program disturb problem involve applying varying biases to the gates of unselected cells. But as with solutions that pre-charge the drain and/or source nodes of unselected cells, applying variable biases to the gates can increase pre-charge and set up times and can increase the overall power consumption.